Parasitic-aware blockage

ABSTRACT

A parasitic-aware blockage structure is provided to replace a detailed blockage structure for use in connection with a capacitance extraction operation. The parasitic-aware blockage structure includes one or more parasitic-aware blockage polygons, each representing a plurality of polygons of the detailed blockage structure. The parasitic-aware blockage polygons can be formed by expanding and merging the polygons of the detailed blockage structure. Physical information is associated with each of the parasitic-aware blockage polygons, wherein the physical information defines physical characteristics of the polygons of the detailed blockage structure. Capacitance error information may also be associated with each of the parasitic-aware blockage polygons, specifying capacitive errors of the parasitic-aware blockage polygons with respect to the polygons of the detailed blockage structure.

FIELD OF THE INVENTION

The present invention relates to a parasitic-aware blockagerepresentation generated from a detailed layout, wherein theparasitic-aware blockage representation facilitates accurate andefficient parasitic capacitance extraction.

RELATED ART

FIG. 1 is a block diagram illustrating a top level design of anintegrated circuit chip 100. Different blocks 101, 102 and 103 areincluded in the top level chip design. The various blocks 101-103 aretypically designed in isolation from one another, such that all of thegeometries of an individual block may not be available/complete whilethe top level design is being performed. Thus, a subset of the blockgeometries is included in a simulation for the top level design. Ingeneral, the terminal connections of the various blocks 101-103 areknown, and are used to establish the required connections between theblocks. In the example illustrated by FIG. 1, block 101 includesterminal connections 101A, 101B and 101C, and block 102 includesterminal connections 102A, 102B and 102C. A place and route method isused to establish connections 111, 112 and 113 between terminalconnections 101A, 101B and 101C and terminal connections 102A, 102B and102C, respectively. In the illustrated example, the connections 111-113extend over circuit block 103, which is positioned between blocks 101and 102 in the top level design. Block 103 includes underlyingconductive structures 110, which result in parasitic capacitances on theconnections 111-113. These parasitic capacitances, which can affect thetransmission of signals on connections 111-113, must be calculated inorder to ensure adequate performance of the signals transmitted onconnections 111-113. The presence of underlying conductive structures110 can also affect the resistances of connections 111-113.

In order to determine the parasitic capacitances associated withconnections 111-113, a parasitic capacitance extraction operation isperformed, wherein the underlying conductor structure 110 of block 103is effectively grounded, and the parasitic capacitances between theunderlying conductor structure 110 and the connections 111-113 arecalculated, based on the physical characteristics of the top leveldesign. These calculated parasitic capacitances are used to estimate thecapacitance effect of the underlying conductor structure 110 on theconnections 111-113.

The pattern used to represent the underlying conductor structure 110 forpurposes of parasitic capacitance extraction is referred to as‘blockage’ (because this pattern may block the place and route methodfrom placing other interconnect structures at the same locations).

In parasitic capacitance extraction, blockage provides a physicalrepresentation of layout 110 to be added in the future. Examples include(1) blockage for standard cells and (2) blockage for macro blocks thatwill ultimately be included in gate-level designs. The blockagegeometries provide a means to estimate the impact of the future layouton the resistance and capacitance of the existing layout in a design.Spacing or density dependent process variations, which impact resistanceand capacitance, are computed based on the blockage polygons. Blockagegeneration and extraction is an important aspect of general gate-levelextraction and physical design. Blockage is typically generated in thephysical domain.

FIG. 2A illustrates the underlying conductor structure 110 as a pattern200A of conductors (including cell contacts 201-205, shown as shadedregions). Pattern 200A corresponds with the exact representation of thelayout shapes of one or more metal layers located below connections111-113. Note that this detailed pattern 200A may be used as theblockage for the parasitic capacitance extraction process. Pattern 200Acontains many small geometries, which will result in an accurateparasitic capacitance extraction. However, the many small geometries ofblockage pattern 200A will undesirably result in a relatively slow(long) parasitic capacitance extraction process.

At another extreme, the underlying conductor structure 110 isrepresented by one or more simple geometries (e.g. plates) that coverthe region where the future layout is to be placed. FIG. 2B illustratesa simple blockage pattern 200B, which represents the underlyingconductor structure 110 as a solid conductive plate. In this embodiment,the simple structure of blockage pattern 200B advantageously results ina relatively fast parasitic capacitance extraction process. However, theaccuracy of the parasitic capacitance extraction process is much lowerwhen using blockage pattern 200B, with a decreased correlation betweenthe blockage parasitics associated with the blockage pattern 200B andthe parasitics ultimately contributed by the detailed layout pattern200A.

The disadvantages of the aforementioned method for generating theblockage pattern 200B is (1) it does not explicitly consider theelectrical characteristics of the underlying layout 110, and (2) it doesnot capture electrical information associated with the underlyingpolygons that can be used for faster or more accurate extraction.Consequently, existing methods for blockage generation in the physicaldomain are sub-optimal with respect to the speed and/or accuracy ofparasitic extraction, and no mechanism exists to selectively optimizethis speed vs. accuracy trade-off, taking into account the parasiticimpact of the blockage. It would therefore be desirable to have improvedmethods for creating blockage with a desired speed or accuracy for agiven application.

SUMMARY

Accordingly, the present invention provides a parasitic-aware blockagestructure to replace a detailed blockage layout structure for use inconnection with a capacitance extraction operation. The parasitic-awareblockage structure includes one or more parasitic-aware blockagepolygons, each representing a plurality of polygons of the detailedblockage layout structure. The parasitic-aware blockage polygons can beformed by iteratively expanding and merging the polygons of the detailedblockage layout structure. Physical information is associated with eachof the parasitic-aware blockage polygons, wherein the physicalinformation defines physical characteristics of the polygons of thedetailed blockage structure. Capacitance error information may also beassociated with each of the parasitic-aware blockage polygons,specifying capacitive errors of the parasitic-aware blockage polygonswith respect to the polygons of the detailed blockage layout structure.

Coupling capacitance error information may also be associated with eachof the parasitic-aware blockage polygons. The coupling capacitance errorspecifies differences in the coupling capacitances between conductorsthat are fabricated adjacent to the parasitic-aware blockage polygons,when compared with the coupling capacitances between the sameconductors, when fabricated adjacent to the detailed blockage layoutstructure.

Resistance error information may also be associated with each of theparasitic-aware blockage polygons, wherein the resistance errorinformation specifies differences in the resistances of conductorsfabricated adjacent to the parasitic-aware blockage polygons (in thesame metal layer), when compared with the resistances of the sameconductors, when fabricated adjacent to the detailed blockage layoutstructure (in the same metal layer).

The present invention will be more fully understood in view of thefollowing description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a top level design of anintegrated circuit chip.

FIG. 2A is a block diagram illustrating a detailed blockage pattern thatcan be used for parasitic capacitance extraction in connection with thetop level design of FIG. 1.

FIG. 2B is a block diagram illustrating a simple blockage pattern thatcan be used for parasitic capacitance extraction in connection with thetop level design of FIG. 1.

FIG. 3 is a block diagram illustrating parasitic-aware blockage patternthat can be used for parasitic capacitance extraction in accordance withone embodiment of the present invention.

FIG. 4 is a block diagram of an exemplary original detailed blockagelayout.

FIG. 5 is a block diagram of an exemplary predicted neighboringconductor layout, which may be located adjacent to the original detailedblockage layout of FIG. 4.

FIG. 6 is a flow diagram that describes a method for generatingparasitic-aware blockage structures from a detailed blockage layout inaccordance with one embodiment of the present invention.

FIG. 7 is a flow diagram illustrating steps for determining predictedneighboring layout shapes in accordance with step 601 of FIG. 6, inaccordance with one embodiment.

FIG. 8 is a block diagram illustrating top and cross sectional views ofan original blockage layout shape of FIG. 4 and a predicted neighboringconductor shape of FIG. 5.

FIG. 9 is a flow diagram illustrating a method for creatingparasitic-aware blockage shapes in accordance with step 604 of FIG. 6,in accordance with one embodiment.

FIG. 10A is a block diagram illustrating the original blockage layoutshapes of FIG. 4 expanded by a bloat factor in accordance with step 901of FIG. 9.

FIG. 10B is a block diagram illustrating the expanded original blockageshapes of FIG. 10A, which are cropped to eliminate portions locatedoutside of an original boundary of the original blockage layout shapes,in accordance with step 902 of FIG. 9.

FIG. 10C is a block diagram illustrating resulting merged portions ofthe expanded and cropped original blockage layout shapes of FIG. 10B, inaccordance with step 903 of FIG. 9.

FIG. 10D is a block diagram illustrating parasitic-aware blockageshapes, which are formed from the original blockage layout shapes andthe merged portions of FIG. 10C in accordance with one embodiment.

FIGS. 11A, 11B, 11C and 11D are block diagrams illustrating the creationof parasitic-aware blockage shapes from the original blockage layoutshapes of FIG. 4, using different bloat factors than those used inconnection with FIGS. 10A-10D.

FIGS. 12A, 12B, 12C and 12D are block diagrams illustrating the creationof parasitic-aware blockage shapes from the original blockage layoutshapes of FIG. 4, using different bloat factors than those used inconnection with FIGS. 10A-10D and FIGS. 11A-11D.

FIG. 13 is a flow diagram illustrating a method for generatingcapacitance data for parasitic-aware blockage shapes in accordance withstep 605 of FIG. 6, in accordance with one embodiment.

FIG. 14A is a block diagram illustrating one method for determining aneffective overlap area for generating the capacitance data in accordancewith the method of FIG. 13.

FIG. 14B is a block diagram illustrating an alternate method fordetermining an effective overlap area for generating the capacitancedata in accordance with the method of FIG. 13.

FIG. 15 is a flow diagram illustrating an alternate method fordetermining capacitive errors associated with parasitic-aware blockageshapes.

FIG. 16 is a graph illustrating time required to extract parasiticcapacitances versus the accuracy of the parasitic capacitance extractionfor detailed original blockage layout shapes, simple blockage layoutshapes and parasitic-aware blockage layout shapes.

FIG. 17 is a graph illustrating time required to extract the parasiticcapacitances versus the accuracy of the associated resistances fordetailed original blockage layout shapes, simple blockage layout shapesand parasitic-aware blockage layout shapes.

FIG. 18 is a block diagram of a simplified representation of anexemplary digital ASIC design flow including the processes fordetermining parasitic-aware blockage shapes and extracting parasiticcapacitances between the parasitic-aware blockage shapes and predictedlayout shapes.

DETAILED DESCRIPTION

In general, the present invention provides a parasitic-aware blockagerepresentation generated from an underlying detailed layout, wherein theparasitic-aware blockage facilitates accurate and efficient parasiticcapacitance extraction. The parasitic-aware blockage representationincludes one or more physical blockage polygons and/or holes, which aregenerated based on physical and electrical rules. Each physical blockagepolygon includes associated physical and/or electrical information toaccurately capture the characteristics of the associated detailedlayout. Parasitic-aware blockage is generated based on any of followingcriteria: (1) width, spacing, uniformity, and/or sparsity of theunderlying detailed layout, (2) ground capacitance errors between theblockage and nearby conductors, (3) coupling capacitance errors betweentwo signal conductors near the blockage due to blockage conductorshielding, and (4) resistance errors due to spacing or density dependentprocess variations.

In one embodiment, the parasitic-aware blockage can be generated usingan iterative process, wherein the number of polygons in theparasitic-aware blockage is minimized while meeting an error constraint.

In one embodiment, information associated with the parasitic-awareblockage can include: (1) the density of the underlying polygons of thedetailed layout, (2) statistics on the X/Y width and spacing of theunderlying polygons of the detailed layout (e.g. average, minimum,maximum), and (3) the level of potential error versus the underlyingpolygons of the detailed layout.

In accordance with one embodiment, extraction simultaneously leveragesparasitic-aware blockage geometries and their associated data to providea tunable speed-versus-accuracy trade-off. In this manner, theparasitic-aware blockage representation provides a means to obtain adesired extraction speed or accuracy for a given application.

The present invention will now be described in more detail.

FIG. 3 is a block diagram illustrating a parasitic-aware blockagepattern 300, which is generated from the detailed conductor layout 200Aof FIG. 2A, in accordance with one embodiment of the present invention.Parasitic-aware blockage pattern 300 simplifies the various smallconductors of the detailed layout 200A into a plurality of polygons301-322. Note that in the illustrated embodiments, the cell contacts201-205 are not modified in the parasitic-aware blockage pattern 300(thereby allowing for connections to these cell contacts). Althoughpolygons 301-322 are squares/rectangles in the illustrated embodiments,it is understood that other polygons can be used in other embodiments.

As described in more detail below, information is associated with eachof the polygons 301-322, wherein this information defines variouscharacteristics of the associated conductors of the detailed conductorlayout 200A. This information can include, for example, the density ofthe associated conductors of the detailed layout 200A, statistics of theX/Y width and spacing of the associated conductors of the detailedlayout 200A (e.g., average width/spacing, minimum width/spacing, maximumwidth spacing), and level of potential RC error versus the associatedconductors of the detailed layout 200A.

When performing the parasitic capacitance extraction, the polygons301-322 and their associated information are simultaneously used todetermine the parasitic capacitances to conductors that extend over theparasitic aware blockage pattern 300. As will become apparent in view ofthe subsequent description, the use of polygons 301-322 (and theirassociated information) provide a more accurate parasitic capacitanceextraction result than the simple blockage 200B, and also provide afaster parasitic capacitance extraction runtime than the detailed layoutblockage 200A.

A specific example of parasitic-aware blockage generation will now bedescribed. This example can be used to generate any of the polygons301-322 of FIG. 3.

FIG. 4 is a block diagram 400 of an original (detailed) blockage layout400, which includes conductive elements 401-406. The collection ofshapes included in the original detailed blockage layout 400 may begenerally identified as S_(OB). The detailed blockage layout 400generally corresponds with conductors in the detailed layout blockage200A. The various dimensions of conductive elements 401-406 areillustrated as generic units. Thus, detailed blockage layout 400 coversa 7×7 grid. Original conductive elements 401-403 each have a width of 1unit along the x-axis, and a width of 7 units along the y-axis. Originalconductive elements 404 and 405 each have a width of 1 unit along thex-axis and a width of 1 unit along the y-axis. Original conductiveelement 406 has a width of 1 unit along the x-axis and a width of 2units along the y-axis.

FIG. 5 is a block diagram of a predicted neighboring conductor layout500, which includes conductive elements 501-506. Conductive elements501-506 represent conductors that may surround (e.g., be routed over)the original blockage layout 400. The collection of shapes included inthe predicted neighboring layout 500 may be generally identified asS_(PRED). The predicted conductor layout 500 may generally correspondwith the connector elements 111-113 of FIG. 1. The outer perimeter ofdetailed blockage layout 400 (i.e., the above-described 7×7 grid) isgenerally illustrated as original box B_(O) in FIG. 5.

FIG. 6 is a flow diagram 600 that describes a method for generatingparasitic-aware blockage structures from a detailed blockage layout inaccordance with one embodiment of the present invention. Initially, thepredicted shapes S_(PRED) surrounding the original blockage layoutshapes S_(OB) are determined/created (Step 601).

FIG. 7 is a flow diagram illustrating steps 701-702 that can beperformed to implement the process of Step 601, in accordance with oneembodiment. A bounding box (BB_(OB)) is created by bloating (expanding)the original box B_(O) that defines the outer boundaries of the originalblockage layout shapes S_(OB) (Step 701). In the described embodiments,the original box B_(O) is bloated beyond the outer boundaries of theoriginal blockage layout shapes S_(OB) by a factor specified by amaximum capacitive interaction distance. FIG. 5 illustrates one exampleof an original box B_(O) and a corresponding bounding box BB_(OB).

The predicted shapes S_(PRED) are then selected to include shapes havinga minimum width and a minimum spacing within the bounding box (Step702). The predicted shapes S_(PRED) can be located within the boundingbox on the layer above the original blockage layout shapes S_(OB), onthe layer below the original blockage layout shapes S_(OB), and/or thesame layer as the original blockage layout shapes S_(OB). Predictedshapes S_(PRED) on the same layers as the original layout shapes S_(OB)are only added if they do not violate the processes minimum spacingrules. That is, the predicted shapes S_(PRED) must not overlap or be tooclose to the original layout shapes S_(OB).

Returning to FIG. 6, capacitance data (C_(OB)) for the original layoutshapes (S_(OB)) to the predicted shapes (S_(PRED)) is generated in step602. FIG. 8 is a block diagram illustrating top and cross sectionalviews of original blockage layout shape 401 and predicted shape 502. Thecapacitance between the original blockage layout shape 401 and thepredicted shape 502 can be determined from the overlap area (A) betweenthese shapes, the thickness (T) of the dielectric material 801 betweenthese shapes, and the dielectric constant (s) of the dielectric material801 between these shapes. More specifically, the capacitance (C_(OB))between original blockage layout shape 401 and predicted shape 502 canbe determined as (E*A)/T. The capacitance (C_(OB)) is determined betweeneach original blockage layout shape (S_(OB)) and each of the predictedshapes (S_(PRED)). Although a relatively simple method for calculatingthe capacitance (C_(OB)) is described, it is understood that otherembodiments can use any common capacitance modeling technique, includingmore complex analytic formulas, pattern-matching capacitance modelingapproaches, and field solver based modeling approaches.

Initial bloat factors (BF) are then selected (Step 603), wherein thebloat factors specify dimensions by which the original blockage layoutshapes (S_(OB)) are to be expanded to create the parasitic-awareblockage shapes S_(PAB). In accordance with one embodiment, a firstbloat factor (B_(SMALL)) is applied to small original blockage layoutshapes, and a second bloat factor (B_(LARGE)) is applied to largeroriginal blockage layout shapes. In the example of FIG. 4, originalblockage layout shapes 404-406 are considered to be small shapes subjectto the first bloat factor B_(SMALL), while original blockage layoutshapes 401-403 are considered to be large shapes subject to the secondbloat factor B_(LARGE). In one embodiment, large shapes are defined asthose shapes that traverse at least a certain percentage (e.g., 50%,75%, 100% of the lateral dimensions of the original box B_(O)). Inanother embodiment, large shapes are defined as those shapes having alargest dimension that exceeds a certain absolute length. In the exampleof FIG. 4, large shapes could be defined as those shapes having anabsolute length greater than 4 units along either the X or Y axis. Inyet another embodiment, a combination of these factors can be used tospecify large shapes. In the simplified examples described herein, thefirst bloat factor B_(SMALL) can have values of 1.0 unit and 0.5 units,and the second bloat factor B_(LARGE) can also have values of 1.0 unitand 0.5 units. However, it is understood that other bloat factors (andother numbers of bloat factors) can be used in other embodiments.

Parasitic-aware blockage shapes (S_(PAB)) are then created by applyingthe selected bloat factors B_(SMALL) and B_(LARGE) to the originalblockage layout shapes S_(OB) (Step 604).

FIG. 9 is a flow diagram illustrating a method for implementing step 604in accordance with one embodiment. The original blockage layout shapes401-406 are expanded by an associated bloat factor (B_(SMALL),B_(LARGE)), which is determined by the size of the original blockagelayout shapes (small/large) (Step 901). FIG. 10A is a block diagramillustrating the original blockage layout shapes 401-406 expanded by abloat factor of 0.5 units (B_(SMALL)=B_(LARGE)=0.5), thereby creatingcorresponding bloated shapes 401A-406A. The portions of the bloatedshapes 401A-406A that protrude beyond the halo of the original blockagelayout shapes 400 (e.g., outside of original box B_(O)) are then removed(Step 902). FIG. 10B is a block diagram illustrating the resultingbloated shapes 401B-406B, which remain after step 902. Any portions ofthe resulting bloated shapes 401B-406B that were bloated into contactalong a single axis are then merged, and any unmerged, unoriginal shapesare eliminated (Step 903). FIG. 10C illustrates the resulting mergedportions 1001-1002 from step 903, along with the original blockagelayout shapes 401-406. FIG. 10D illustrates the resultingparasitic-aware blockage shapes P1-P4, which are formed from theoriginal blockage layout shapes 401-406 and the merged portions1001-1002. In the illustrated example, parasitic-aware blockage shape P1includes original blockage layout shapes 401-402 and merged portion1001; parasitic-aware blockage shape P2 includes a portion of originalblockage layout shape 403, as well as original blockage shapes 404-405and merged portion 1002; parasitic-aware blockage shape P3 includes aportion of original blockage layout shape 403; and, parasitic-awareblockage shape P4 includes a portion of original blockage layout shape403, as well as original blockage shape 406. Other combinations oforiginal blockage layout shapes 401-406 and merged portions 1001-1002can be used to form other parasitic-aware blockage shapes in otherembodiments. In general, the original blockage layout shapes and mergedportions are combined in a manner that minimizes the number ofparasitic-aware blockage shapes.

Physical information is then associated with each of the createdparasitic-aware blockage shapes P1-P4 (Step 904). This physicalinformation identifies characteristics of the original blockage layoutshapes 400 (S_(OB)) underlying each of the parasitic-aware blockageshapes P1-P4, including, for example, X-width parameters, Y-widthparameters, X-spacing parameters, Y-spacing parameters and density. Inthe example illustrated by FIGS. 10A-10D, parasitic-aware blockageshapes (S_(PAB)) P1-P4 exhibit the physical information as set forthbelow in Tables 1-4.

TABLE 1 Physical Info for Parasitic-aware blockage shape P1 Average Std.Dev. Min. Max X-width 1 0 1 1 Y-width 7 0 7 7 X-spacing 1 0 1 1Y-spacing 0 0 0 0 Density 2/3 — — —

TABLE 2 Physical Info for Parasitic-aware blockage shape P2 Average Std.Dev. Min. Max X-width 1.67 0.58 1 2 Y-width 2 1.15 1 3 X-spacing 0.330.58 0 1 Y-spacing 0.5 0.7 0 1 Density 5/6 — — —

TABLE 3 Physical Info for Parasitic-aware blockage shape P3 Average Std.Dev. Min. Max X-width 1 0 1 1 Y-width 2 0 2 2 X-spacing 0 0 0 0Y-spacing 0 0 0 0 Density 1 — — —

TABLE 4 Physical Info for Parasitic-aware blockage shape P4 Average Std.Dev. Min. Max X-width 2 0 2 2 Y-width 2 0 2 2 X-spacing 0 0 0 0Y-spacing 0 0 0 0 Density 1 — — —

Thus, in accordance with Table 2, the portions of original blockagelayout shapes 403, 404 and 405 covered by parasitic-aware blockage shapeP2 exhibit a maximum X-width of 2 units, a minimum X-width of 1 unit, anaverage X-width of 1.67 units (i.e., ((2 units*⅓)+(1 unit×⅓)+(2units*⅓)), and a standard deviation of 0.58 (i.e., sqrt((2−1.67)²+(1−1.67)²+(2−1.67)²)/(3−1)). The X-width (and Y-width) valuesof the other parasitic-aware blockage shapes are calculated in a similarmanner.

Also in accordance with Table 2, the portions of original blockagelayout shapes 403, 404 and 405 covered by parasitic-aware blockage shapeP2 exhibit a maximum X-spacing of 1 unit, a minimum X-spacing of 0 unit,an average X-spacing of 0.33 units (i.e., ((0 units*⅓)+(1 unit×⅓)+(0units*⅓)), and a standard deviation of 0.58 (i.e., sqrt((0−0.33)²+(1−0.33)²+(0−0.33)²)/(3−1)). The X-spacing (and Y-spacing)values of the other parasitic-aware blockage shapes are calculated in asimilar manner.

Also in accordance with Table 2, the portions of original blockagelayout shapes 403, 404 and 405 covered by the parasitic-aware blockageshape P2 have an area that is ⅚ of the area of the parasitic-awareblockage shape P2 (for a density of ⅚). The densities of the otherparasitic-aware blockage shapes are calculated in a similar manner.

As described in more detail below, the bloat factors (B_(SMALL),B_(LARGE)) can be iteratively modified, if necessary, thereby resultingin different parasitic-aware blockage shapes (S_(PAB)), which providedifferent representations of the original blockage layout shapes(S_(OB)). FIGS. 11A-11D are block diagrams illustrating the creation ofparasitic-aware blockage shapes from the original blockage layout shapes401-406, when using the bloat factors B_(SMALL)=1.0, B_(LARGE)=0.5. Asillustrated in FIG. 11A, the small shapes 404-406 are bloated by 1.0unit to create corresponding bloated shapes 404C-406C (and the largeshapes 401-403 are bloated by 0.5 units to create bloated shapes401A-403A). As shown in FIG. 11B, the portions of bloated shapes401A-403A and 404C-406C extending outside of the original box (B_(O))are eliminated, thereby leaving corresponding bloated shapes 401B-403Band 404D-406D. FIG. 11C illustrates the overlapping bloated regions1102-1103, which are located adjacent to original blockage layout shapes403-406 (as well as the overlapping bloated region 1001, which islocated between original blockage shapes 401-402). FIG. 11D illustratesthe resulting parasitic aware blocking shapes P1 and P5, wherein theparasitic aware blocking shapes P1 of FIGS. 10D and 11D are identical,and the parasitic aware blocking shape P5 of FIG. 11D, which includesoriginal layout shapes 403-406 and bloated regions 1102-1103, and hasthe physical characteristics set forth in Table 5 below.

TABLE 5 Physical Info for Parasitic-aware blockage shape P5 Average Std.Dev. Min. Max X-width 1.57 0.53 1 2 Y-width 2.75 2.87 1 7 X-spacing 0.430.53 0 1 Y-spacing 0.75 0.96 0 2 Density 11/14 — — —

FIGS. 12A-12D are block diagrams illustrating the creation ofparasitic-aware blockage shapes from the original blockage layout shapes401-406, when using bloat factors B_(SMALL)=1.0, B_(LARGE)=1.0. Asillustrated in FIG. 12A, shapes 401-406 are each bloated by 1.0 unit tocreate corresponding bloated shapes 401E-406E. As shown in FIG. 12B, theportions of bloated shapes 401E-406E extending outside of the originalbox (B_(O)) are eliminated, thereby leaving corresponding bloated shapes401F-406F. FIG. 12C illustrates the overlapping bloated regions1201-1204, which are located adjacent to original blockage layout shapes401-406. FIG. 12D illustrates the resulting parasitic aware blockageshape P6, which includes the original blockage layout shapes 401-406 andthe bloated regions 1201-1204, and has the physical characteristics setforth in Table 6 below. Note that the parasitic-aware blockage shape P6physically covers the entire original box B_(O).

TABLE 6 Physical Info for Parasitic-aware blockage shape P6 Average Std.Dev. Min. Max X-width 1.19 0.40 1 2 Y-width 3.19 3.41 0 7 X-spacing 0.501.43 1 2 Y-spacing 3.21 3.45 0 7 Density 25/42 — — —

As illustrated by FIGS. 10A-10D, 11A-11D and 12A-12D, the resultingparasitic-aware blockage shapes become more detailed as the bloatfactors B_(SMALL), B_(LARGE) are reduced. In accordance with oneembodiment, the parasitic-aware blockage shapes (S_(PAB)) are initiallygenerated using the maximum bloat factors (e.g., B_(SMALL)=1.0 andB_(LARGE)=1.0). As a result, a relatively simple parasitic-awareblockage shape (e.g., parasitic-aware blockage shape P6 of FIG. 12D) isinitially created. If this simple parasitic-aware blockage shape isdetermined to have an acceptable associated error (as described below),then it is not necessary to generate more complicated parasitic-awareblockage shapes (e.g., parasitic-aware blockage shapes P1-P4 of FIG.10D, or P1 and P5 of FIG. 11D).

Returning now to FIG. 6, after the parasitic-aware blockage shapes(S_(PAB)) have been generated, capacitance data (C_(PAB)) is generatedfor the parasitic-aware blockage shapes (S_(PAB)) and the predictedlayout shapes (S_(PRED)) (Step 605). In accordance with one embodiment,this capacitance data (C_(PAB)) is generated using the physicalinformation associated with each of the parasitic-aware blockage shapes.FIG. 13 is a flow diagram illustrating a method for implementing step605 in accordance with one embodiment. First, an effective overlap area(A_(EFF)) is determined between each parasitic-aware blockage shape(S_(PAB)) and each of the predicted layout shapes (S_(PRED)) (Step1301).

The effective overlap area (A_(EFF)) of a parasitic-aware blockage shape(S_(PAB)) with respect to a predicted layout shape (S_(PRED)) can bedetermined in various manners using the physical data associated withthe parasitic-aware blockage shape (S_(PAB)).

FIG. 14A is a block diagram illustrating one method 1301A forimplementing step 1301 of FIG. 13. In this method 1301A, the effectiveoverlap area A_(EFF) is set equal to the actual overlap area (A) betweenthe parasitic-aware blockage shape (S_(PAB)) and the predicted layoutshape (S_(PRED)), multiplied by the density of the parasitic awareblockage shape (S_(PAB)). As described above, the density of theparasitic aware blockage shape S_(PAB) is determined during step 604(FIG. 6).

FIG. 14B is a block diagram illustrating an alternate method 1301B forimplementing step 1301 of FIG. 13. In this method 1301B, the effectiveoverlap area A_(EFF) is set equal to the actual overlap area (A) betweenthe parasitic-aware blockage shape (S_(PAB)) and the predicted layoutshape (S_(PRED)), multiplied by the following factor:(Average X-width of S _(PAB)+Average Y-width of S _(PAB))/(AverageX-width of S _(PAB)+Average Y-width of S _(PAB)+(Average X-spacing of S_(PAB)+Average Y-spacing of S _(PAB))

As described above, the various widths and spacings of theparasitic-aware blockage shape S_(PAB) are determined during step 604(FIG. 6).

Returning now to FIG. 13, after the effective overlap area (A_(EFF)) isdetermined, the effective capacitance (C_(EFF)) between each parasiticaware blockage shape (S_(PAB)) and each of the predicted layout shapes(S_(PRED)) is calculated (Step 1302) using the equationC_(EFF)=(∈*A_(EFF))/T, wherein the variables ∈ and T are described abovein connection with FIG. 8.

Although specific methods for determining the effective overlap area ofa parasitic aware blockage shape (S_(PAB)) and a predicted layout shape(S_(PRED)) have been described above, it is understood that otherpossible uses of the physical parameters associated with the parasiticaware blockage shape (S_(PAB)) can be used to determine the effectivecapacitance C_(EFF), depending on the particular capacitance model usedto determine the effective capacitance C_(EFF). Thus, while a parallelplate model for determining capacitance is described herein forillustrative purposes, it is understood that any baseline capacitancemodeling technique can be used, including more complex analyticalformulas, pattern-matching capacitance modeling approaches, and fieldsolver-based modeling approaches. The usage of the physical andelectrical parameters stored on the parasitic-aware blockage shapesdepends on the baseline capacitance modeling technique used.

Returning now to FIG. 6, after the above-described effectivecapacitances C_(EFF) have been determined, errors (E_(PAB)) between theeffective capacitances (C_(EFF)) and the corresponding actualcapacitances (C_(OB)) (calculated during step 602) are determined (Step606). More specifically, the capacitive error associated with each ofthe parasitic-aware blockage shapes (S_(PAB)) is determined. Forexample, assume that the original blockage layout shapes 401-402 arerepresented by the parasitic-aware blockage shape P1 (FIG. 10D), andthat the effective capacitances between the parasitic-aware blockageshape P1 and the predicted layout shapes 502 and 503 that overlie overthe parasitic-aware blockage shape P1 are represented by C_(EFF) 1 andC_(EFF) 2, respectively. Further assume that the predicted layout shape502 extends over original blockage layout shape 401 (with acorresponding capacitance represented by C_(OB) 1), and the predictedlayout shape 503 extends over original blockage layout shape 503 (with acorresponding capacitance represented by C_(OB) 2). In this case, thecapacitive error E_(PAB) associated with the parasitic-aware blockageshape P1 could be defined as follows.E _(PAB)=((C _(EFF)1+C _(EFF)2)−(C _(OB)1+C _(OB)2))/(C _(OB)1+C _(OB)2)

FIG. 15 is a flow diagram 1500 illustrating an alternate method fordetermining the capacitive errors E_(PAB) associated with theparasitic-aware blockage shapes (S_(PAB)). Initially, a minimumcapacitance (C_(MIN)) is determined based on the physical informationassociated with each of the parasitic-aware blockage shapes (Step 1501).The minimum capacitance (C_(MIN)) is defined as follows:C _(MIN)=(∈*A _(MIN))/Twherein A_(MIN) is a minimum overlap area between the parasitic-awareblockage shape (S_(PAB)) and the overlying predicted layout shapes(S_(PRED)). The minimum overlap area A_(MIN) can be defined as follows.A _(DEN)=Overlap area between predicted layout shape (S _(PRED)) and theparasitic-aware blockage shape (S _(PAB))*(Min. X-Width ofparasitic-aware blockage shape+Min. Y-Width of parasitic-aware blockageshape)/(Min. X-Width of parasitic-aware blockage shape+Min. Y-Width ofparasitic-aware blockage shape+Min. X-Spacing of parasitic-awareblockage shape+Min. Y-Spacing of parasitic-aware blockage shape)

A maximum capacitance (C_(MAX)) is then determined based on the physicalinformation associated with each of the parasitic-aware blockage shapes(Step 1502). The maximum capacitance (C_(MAX)) is defined as follows:C _(MAX)=(∈*A _(MAX))/Twherein A_(MAX) is a maximum overlap area between the parasitic-awareblockage shape (S_(PAB)) and the overlying predicted layout shapes(S_(PRED)). The maximum overlap area A_(MAX) can be defined as follows.A _(MAX)=Overlap area between predicted layout shape (S _(PRED)) and theparasitic-aware blockage shape (S _(PAB))*(Max. X-Width ofparasitic-aware blockage shape+Max. Y-Width of parasitic-aware blockageshape)/(Max. X-Width of parasitic-aware blockage shape+Max. Y-Width ofparasitic-aware blockage shape+Max. X-Spacing of parasitic-awareblockage shape+Max. Y-Spacing of parasitic-aware blockage shape)

A first error (Error1) is then calculated between the effectivecapacitance C_(EFF) of the parasitic-aware blockage shape (S_(PAB)) andthe minimum capacitance C_(MIN) (Step 1503). For example, Error1 may beequal to (C_(EFF)−C_(MIN))/C_(EFF).

A second error (Error2) is then calculated between the effectivecapacitance C_(EFF) of the parasitic-aware blockage shape (S_(PAB)) andthe maximum capacitance C (Step 1504). For example, Error2 may be equalto (C_(EFF)−C_(MAX))/C_(EFF).

The capacitance error E_(PAB) is then selected to be the larger ofError1 or Error 2 (Step 1505).

While the example of FIG. 15 uses the physical dimensions of theparasitic-aware blockage shapes to determine the capacitance errorE_(PAB), it is understood that this capacitance error E_(PAB) canalternately be determined using the standard deviations of the physicaldimensions of the parasitic-aware blockage shapes. For example, ratherthan determining the minimum overlap area A_(MIN) using the minimumX-width, minimum Y-width, minimum X-spacing and minimum Y-spacing in themanner described above, the minimum overlap area A_(MIN) can bedetermined using an “average−N*sigma” approach. For example, assume thatthe X-width has an average of 1.67 and a standard deviation of 0.58(see, parasitic-aware blockage shape P2 of Table 2). Using an“average−1*sigma” approach, the term “min X-width” in the A_(MIN)formula becomes “average−1*sigma”, which is equal to 1.67−0.58=1.09.Note that this is less conservative than using the minimum X-width valueof 1. The minimum Y-width, minimum X-spacing and minimum Y-spacing cansimilarly be replaced with “average−1*sigma” values in the A_(MIN)formula. In practice, the “average−N*sigma” approach works better if thenumber of underlying shapes is large, whereas the approach using thevarious minimum values works better if the number of underlying shapesis small. In accordance with this embodiment, the maximum area overlap Acan be determined in a similar manner using “average+N*sigma”calculations.

Returning now to FIG. 6, the capacitance error E_(PAB) for eachparasitic-aware blockage shape is compared with a predetermined errorthreshold (E_(THRESHOLD)) (Step 607). If the capacitance error E_(PAB)is less than the predetermined error threshold for each of theparasitic-aware blockage shapes (step 607, YES branch), then each of thecapacitance errors E_(PAB) is associated with its correspondingparasitic aware blockage shape (S_(PAB)) (Step 608). The process thenreturns the parasitic-aware blockage shapes S_(PAB) (along with theirassociated physical information and their associated capacitance errorsE_(PAB)) as the output of the parasitic-aware blockage determinationmethod (Step 609).

However, if the capacitance error E_(PAB) of each parasitic-awareblockage shape is not less than the predetermined error threshold(E_(THRESHOLD)) (Step 607, NO branch), a determination is made whetherall possible bloat factors have been attempted to create theparasitic-aware blockage shapes (Step 610). If not (step 610, NObranch), then the bloat factors (B_(SMALL), B_(LARGE)) are iterativelyadjusted (Step 611), and the process returns to step 604, wherein a newset of parasitic-aware blockage shapes (and associated physicalinformation) are generated using the new bloat factors. In oneembodiment, the bloat factors B_(SMALL) and B_(LARGE) are initially setto their largest values (e.g., B_(SMALL)=B_(LARGE)=1.0, as illustratedby FIGS. 12A-12D). The bloat factor B_(LARGE) is iteratively reduced toits smallest value (while keeping B_(SMALL) at its largest value). Afterthe bloat factor B_(LARGE) reaches its smallest value, the bloat factorsB_(SMALL) and B_(LARGE) are both set to their second largest value, andthe process is repeated.

If all possible bloat factors B_(SMALL) and B_(LARGE) have beenattempted, and the capacitance error E_(PAB) is still greater than thepredetermined threshold error (E_(THRESHOLD)) (step 610, YES branch),then the original blockage layout shapes (S_(OB)) (each having acorresponding capacitance error E_(PAB) of zero) are returned as theresult of the parasitic-aware blockage determination method (Step 612).In this case, the detailed original blockage layout shapes (S_(OB)) areused because it is not possible to provide parasitic-aware blockageshapes that meet the predetermined threshold error (E_(THRESHOLD)).

Although the iteration of the bloat factors B_(SMALL) and B_(LARGE) havebeen described, it is understood that this iteration technique can bereplaced by more efficient discrete optimization methods, such asinteger programming techniques (e.g., branch and bound) in alternateembodiments. In yet other embodiments, different and more numerousclassifications beyond ‘SMALL’ and ‘LARGE’ can be applied to determinebloat factors for the original blockage layout shapes (S_(OB)).

In accordance with one embodiment, a parasitic capacitance extractiontool uses the parasitic-aware blockage shapes (S_(PAB)), the associatedphysical information and the associated capacitance errors E_(PAB)returned by method 600 to calculate parasitic capacitances between theparasitic aware blockage shapes (S_(PAB)) and the predicted layoutshapes (S_(PRED)).

As described above in connection with step 607 (FIG. 6), the capacitanceerror E_(PAB) of each of the parasitic-aware shapes is compared with thepredetermined threshold error (E_(THRESHOLD)). However, in an alternateembodiment, the capacitance errors E_(PAB) for all of theparasitic-aware blockage shapes can be weighted and averaged, and thisweighted average can be compared to a predetermined error threshold(E_(TH)) to determine how to proceed (e.g., to step 608 or step 609).For example, the weighted average of the capacitance errors E_(PAB) forall of the parasitic-aware blockage shapes P1-P4 of FIG. 10D can bedetermined as follows.E _(PAB) _(_) _(ALL)=(E _(PAB) _(_) _(P1) *C _(OB) _(_) _(P1) +E _(PAB)_(_) _(P2) *C _(OB) _(_) _(P2) +E _(PAB) _(_) _(P3) *C _(OB) _(_) _(P3)+E _(PAB) _(_) _(P4) *C _(OB) _(_) _(P4))/(C _(OB) _(_) _(P1) +C _(OB)_(_) _(P2) +C _(OB) _(_) _(P3) +C _(OB) _(_) _(P4))wherein E_(PAB) _(_) _(Pn) is the capacitance error associated with theparasitic-aware blockage shape Pn, and C_(OB) _(_) _(Pn) is thecapacitance of the original blockage shape(s) associated with theparasitic-aware blockage shape Pn. For example, when using theparasitic-aware blockage shapes P1-P4 of FIG. 10D: C_(OB) _(_)_(P1)=C_(OB) of original blockage shape 401+C_(OB) of original blockageshape 402; C_(OB) _(_) _(P2)=C_(OB) of original blockage shape 403*(3/7)+C_(OB) of original blockage shape 404+C_(OB) of original blockageshape 405; C_(OB) _(_) _(P3)=C_(OB) of original blockage shape 403*(2/7); and, C_(OB) _(_) _(P4)=C_(OB) of original blockage shape 403*(2/7)+C_(OB) of original blockage shape 406.

FIG. 16 is a graph 1600 illustrating the time required to extractparasitic capacitances (normalized to the time required to extractparasitic capacitances using the detailed original blockage layoutshapes (S_(OB))) versus the accuracy of the parasitic capacitanceextraction (measured by the percentage of nets having a capacitanceerror of more than 5%). FIG. 17 is a graph 1700 illustrating the timerequired to extract the parasitic capacitances (normalized to the timerequired to extract parasitic capacitances using the detailed originalblockage layout shapes (S_(OB))) versus the accuracy of the associatedresistances (measured by the percentage of nets having a resistanceerror of more than 5%).

As illustrated by FIG. 16, using the original detailed blockage layoutshapes (S_(OB)) results in no nets with a capacitance error greater than5%, with a normalized runtime of 1.0. In contrast, using the simplifiedblockage shapes (see, e.g., FIG. 2B), results in a relatively fastnormalized runtime (essentially 0 normalized runtime) with about 2.4% ofthe nets exhibiting a capacitance error of more than 5%. However, usinga parasitic-aware blockage shapes (S_(PAB)) results in a normalized runtime of about 0.35, and about 0.4% of the nets exhibiting a capacitanceerror greater than 5%. Thus, using parasitic-aware blockage shapes(S_(PAB)) in the manner described above speeds up the parasiticcapacitance extraction process by about 2.9× with respect to thedetailed original blockage layout shapes (S_(OB)). Furthermore, usingthe parasitic-aware blockage shapes (S_(PAB)) in the manner describedabove results in about 6× fewer nets exhibiting a capacitance errorgreater than 5%, when compared with a simple blockage representation.

Similarly, as illustrated by FIG. 17, using the original detailed layoutshapes (S_(OB)) results in no nets with a resistance error greater than5%, with a normalized runtime of 1.0. In contrast, using the simplifiedblockage shapes (see, e.g., FIG. 2B), results in a relatively fastnormalized runtime (essentially 0 normalized runtime) with about 0.024%of the nets exhibiting a resistance error of more than 5%. However,using the parasitic-aware blockage shapes (S_(PAB)) results in anormalized run time of about 0.35, and about 0.0005% of the netsexhibiting a resistance error greater than 5%. Thus, usingparasitic-aware blockage shapes (S_(PAB)) in the manner described aboveresults in about 50× fewer nets exhibiting a resistance error greaterthan 5%, when compared with a simple blockage representation. Moreimprovement in speed and accuracy may be obtained if the parasitic-awareblocking method is applied to blockages representing larger macros.

In an alternate embodiment, the parasitic-aware blockage shapes(S_(PAB)) can be used without the associated physical information, whichmay result in a loss in accuracy, but a faster parasitic capacitanceextraction runtime.

Although particular methods for computing the predicted layout shapes(S_(PRED)) have been described, other possibilities for determining thepredicted layout shapes can be used. For example, the approach used canbe determined based on a pre-characterization of the designs where theparasitic-aware blockage will be used.

The examples described above do not discuss capacitance errors due tothe shielding impact of the blockages, or resistance errors due toprocess variations. These metrics can be evaluated in a manner similarto the capacitances between the predicted layout shapes and theparasitic-aware blockage shapes described in the examples above.

As described above, the parasitic-aware blockage shapes (S_(PAB)) can begenerated based on the physical characteristics of the original blockagelayout shapes (S_(OB)). In accordance with another embodiment, theparasitic-aware blockage shapes (S_(PAB)) can also be generated based oncoupling capacitance errors due to shielding. For example, the couplingcapacitances between the various conductors 501-506 of the predictedlayout shapes (S_(PRED)) are affected by the presence of the underlyingoriginal blockage layout shapes (S_(OB)) 401-406. Replacing the originalblockage layout shapes (S_(OB)) with the parasitic-aware blockage shapes(S_(PAB)) may introduce errors to the coupling capacitances between thepredicted layout shapes (S_(PRED)). To account for these errors, theprocesses described above can be modified in the following manner.

In the method of FIG. 6, the step of determining the ground capacitances(C_(OB)) between the original blockage layout shapes (S_(OB)) and thepredicted layout shapes (S_(PRED)) (step 602) can be replaced with astep of determining the coupling capacitances (CC_(OB)) between thepredicted layout shapes (S_(PRED)) when the original blockage layoutshapes (S_(OB)) are present.

The method of FIG. 6 can further be modified to replace the step ofdetermining the ground capacitances (C_(PAB)) between theparasitic-aware blockage shapes (S_(PAB)) and the predicted layoutshapes (S_(PRED)) (step 605) with a step of determining the couplingcapacitances (CC_(PAB)) between the predicted layout shapes (S_(PRED))when the parasitic-aware blockage shapes (S_(PAB)) are present. In thisembodiment, coupling capacitance errors (E_(CCPAB)) associated with theparasitic-aware blockage shapes (S_(PAB)) are calculated by comparingthe coupling capacitances (CC_(OB)) with the coupling capacitances(CC_(PAB)) (in a manner similar to that described above in connectionwith step 606). If the coupling capacitance errors (E_(CCPAB)) are lessthan a predetermined threshold (in a manner analogous to step 607), thenthe coupling capacitance errors (E_(CCPAB)) are attached to thecorresponding parasitic-aware blockage shapes (S_(PAB)) (in a manneranalogous to step 608).

In accordance with another embodiment, the parasitic-aware blockageshapes (S_(PAB)) can also be generated based on resistance errors due toprocess variations. Due to sub-wavelength lithographic effects, thewidth of a conductor depends on the spacing between the conductor andnearby conductors in advanced process technologies. Due to theplanarization of copper interconnect from the CMP process used in ICfabrication, the thickness of a conductor depends on its width and thewidth/spacing/density of nearby conductors. Because the parasiticaware-blockage shapes (S_(PAB)) may change the width/spacing/density ofother adjacent conductors (in the same metal layer), the parasitic-awareblockage shapes (S_(PAB)) may change the resistances of these adjacentconductors when compared to the resistances resulting from the originalblockage layout shapes (S_(OB)). For example, the resistances ofconductors located by immediately adjacent to the original blockagelayout shapes (S_(OB)) 401-406 are affected by the width/spacing/densityof the original blockage layout shapes (S_(OB)). Replacing the originalblockage layout shapes (S_(OB)) with the parasitic-aware blockage shapes(S_(PAB)) may introduce errors to the resistances of these adjacentconductors. This change in resistance can be viewed as another errorsource for the parasitic-aware blockage shapes (S_(PAB)) that can beoptimized/controlled in the same manner described above for errors inground capacitances between the parasitic-aware blockage shapes and thepredicted layout shapes (S_(PRED)), or in the same manner describedabove for errors in the coupling capacitances between the predictedlayout shapes (S_(PRED)) due to the parasitic-aware blockage shapes. Toaccount for these resistance errors, the processes described above canbe modified in the following manner.

In the method of FIG. 6, the step of determining the ground capacitances(C_(OB)) between the original blockage layout shapes (S_(OB)) and thepredicted layout shapes (S_(PRED)) (step 602) can be replaced with astep of determining the resistances (R_(OB)) of conductors (S_(A))fabricated adjacent to the original blockage layout shapes (S_(OB)). Forexample, the resistance of a conductor (S_(A)) fabricated immediatelyadjacent to original blockage layout shapes 404-406 may be determined.

The method of FIG. 6 can further be modified to replace the step ofdetermining the ground capacitances (C_(PAB)) between theparasitic-aware blockage shapes (S_(PAB)) and the predicted layoutshapes (S_(PRED)) (step 605) with a step of determining the resistances(R_(PAB)) of the conductors (S_(A)) fabricated adjacent to theparasitic-aware blockage shapes (S_(PAB)). In this embodiment,resistance errors (E_(RPAB)) associated with the parasitic-awareblockage shapes (S_(PAB)) are calculated by comparing the resistances(R_(OB)) with the resistances (R_(PAB)) (in a manner similar to thatdescribed above in connection with step 606). If the resistance errors(E_(RPAB)) are less than a predetermined threshold (in a manneranalogous to step 607), then the resistance errors (E_(RPAB)) areattached to the corresponding parasitic-aware blockage shapes (S_(PAB))(in a manner analogous to step 608).

FIG. 18 is a block diagram of a simplified representation of anexemplary digital ASIC design flow including the processes fordetermining parasitic-aware blockage shapes (S_(PAB)) and extractingparasitic capacitances between the parasitic-aware blockage shapes andpredicted layout shapes (S_(PRED)) as described above. At a high level,the process starts with the product idea (step 1800) and is realized inan EDA software design process (step 1810). When the design isfinalized, it can be taped-out (event 1840). After tape out, thefabrication process (step 1850) and packaging and assembly processes(step 1860) occur resulting, ultimately, in finished chips (result1870). In accordance with various embodiments, the above-describedmethods of determining parasitic-aware blockage shapes (S_(PAB)) (aswell as the associated physical information and the correspondingcapacitance errors (E_(PAB))) and performing the parasitic capacitanceextraction, can be implemented in the EDA software design process (step1810).

The EDA software design process (step 1810) is actually composed of anumber of steps 1812-1830, shown in linear fashion for simplicity. In anactual ASIC design process, the particular design might have to go backthrough steps until certain tests are passed. Similarly, in any actualdesign process, these steps may occur in different orders andcombinations. This description is therefore provided by way of contextand general explanation rather than as a specific, or recommended,design flow for a particular ASIC.

A brief description of the components/steps of the EDA software designprocess (step 1810) will now be provided. In one embodiment, one or moresteps of the EDA software design process can be implemented using acomputer-readable medium 1811A, which is read by a computer 1811B. Notethat Astro, AstroRail, CustomSim, ESP, Hercules, IC Compiler, Magellan,Model Architect, Power Compiler, PrimeRail, Proteus, ProteusAF, PSMGen,Saber, StarRC, and System Studio are trademarks of Synopsys, Inc., andCATS, DesignWare, Design Compiler, Formality, HSIM, Leda, NanoSim,Primetime, Syndicated, TetraMAX, VCS, and Vera are registered trademarksof Synopsys, Inc. System design (step 1812): The designers describe thefunctionality that they want to implement, they can perform what-ifplanning to refine functionality, check costs, etc. Hardware-softwarearchitecture partitioning can occur at this stage. Exemplary EDAsoftware products from Synopsys, Inc. that can be used at this stepinclude Model Architect™, Saber™, System Studio™, and DesignWare®products.

Logic design and functional verification (step 1814): At this stage, theVHDL or Verilog code for modules in the system is written and the designis checked for functional accuracy. More specifically, does the designas checked to ensure that produces the correct outputs. Exemplary EDAsoftware products from Synopsys, Inc. that can be used at this stepinclude HSIM®, NanoSim®, CustomSim™, VCS®, VERA®, DesignWare®,Magellan™, Formality®, ESP™ and LEDA® products.

Synthesis and design for test (step 1816): Here, the VHDL/Verilog istranslated to a netlist. The netlist can be optimized for the targettechnology. Additionally, the design and implementation of tests topermit checking of the finished chip occurs. Exemplary EDA softwareproducts from Synopsys, Inc. that can be used at this step includeDesign Compiler®, Power Compiler™, Tetramax®, and DesignWare® products.

Netlist verification (step 1818): At this step, the netlist is checkedfor compliance with timing constraints and for correspondence with theVHDL/Verilog source code. Exemplary EDA software products from Synopsys,Inc. that can be used at this step include Formality®, PrimeTime™, andVCS® products.

Design planning (step 1820): Here, an overall floorplan for the chip isconstructed and analyzed for timing and top-level routing. Exemplary EDAsoftware products from Synopsys, Inc. that can be used at this stepinclude Astro™ and IC Compiler™ products. In accordance with variousembodiments, the above-described methods for determining parasitic-awareblockage shapes (S_(PAB)) (as well as the associated physicalinformation and the corresponding capacitance errors (E_(PAB))) andperforming the parasitic capacitance extraction, can be implemented indesign planning step 1820.

Physical implementation (step 1822): The placement (positioning ofcircuit elements) and routing (connection of the same) occurs at thisstep. In accordance with various embodiments, the above-describedmethods for determining parasitic-aware blockage shapes (S_(PAB)) (aswell as the associated physical information and the correspondingcapacitance errors (E_(PAB))) and performing the parasitic capacitanceextraction, can be implemented during the place and route processassociated with step 1822. Exemplary EDA software products fromSynopsys, Inc. that can be used at this step include the Astro™ and ICCompiler™ products.

Analysis and extraction (step 1824): At this step, the circuit functionis verified at a transistor level, this in turn permits what-ifrefinement. Exemplary EDA software products from Synopsys, Inc. that canbe used at this step include AstroRail™, PrimeRail™, Primetime®, andStar RC/XT™ products. In accordance with various embodiments, theabove-described methods of for determining parasitic-aware blockageshapes (S_(PAB)) (as well as the associated physical information and thecorresponding capacitance errors (E_(PAB))) and performing the parasiticcapacitance extraction, can be implemented in step 1824.

In accordance with one embodiment, a computer readable medium 1811Astores instructions, which when executed by a processor 1811B, willimplement the above-described method(s) for determining parasitic-awareblockage shapes (S_(PAB)) (as well as the associated physicalinformation and the corresponding capacitance errors (E_(PAB))) asdescribed above. If these parasitic-aware blockage shapes (S_(PAB))cause the transmission characteristics of the predicted layout shapes(S_(PRED)) to fall outside of a desired range, then the original ICdesign can be modified in order to change the top level design.

The above-described method(s) for determining parasitic-aware blockageshapes (S_(PAB)) can then be applied to the modified IC design, and theresults can be used to determine whether the transmissioncharacteristics of the predicted layout shapes (S_(PRED)) areacceptable. This process can be repeated until the transmissioncharacteristics of the predicted layout shapes (S_(PRED)) are determinedto be acceptable.

Physical verification (step 1826): At this step various checkingfunctions are performed to ensure correctness for: manufacturing,electrical issues, lithographic issues, and circuitry. Exemplary EDAsoftware products from Synopsys, Inc. that can be used at this stepinclude the Hercules™ product.

Resolution enhancement (step 1828): This step involves geometricmanipulations of the layout to improve manufacturability of the design.Exemplary EDA software products from Synopsys, Inc. that can be used atthis step include Proteus™, ProteusAF™, and PSMGen™ products.

Mask data preparation (step 1830): This step provides the “tape-out”data for production of masks for lithographic use to produce finishedchips. Exemplary EDA software products from Synopsys, Inc. that can beused at this step include the CATS® family of products.

Although illustrative embodiments of the invention have been describedin detail herein with reference to the accompanying figures, it is to beunderstood that the invention is not limited to those preciseembodiments. Thus, the scope of the invention is defined by thefollowing claims and their equivalents.

We claim:
 1. A method for extracting parasitic capacitances associatedwith a detailed blockage structure, the method comprising: deriving oneor more parasitic-aware blockage polygons from the detailed blockagestructure, wherein each of the one or more parasitic-aware blockagepolygons represents a plurality of polygons of the detailed blockagestructure; associating physical information with each of the one or moreparasitic-aware blockage polygons, wherein the physical informationrepresents physical characteristics of the represented plurality ofpolygons of the detailed blocking structure; using a processor toextract parasitic capacitances that exist between the detailed blockingstructure and an adjacent interconnect structure, wherein the processorextracts the parasitic capacitances based on the one or moreparasitic-aware blockage polygons and the associated physicalinformation.
 2. The method of claim 1, wherein the physical informationincludes a density of the detailed blockage structure with respect tothe one or more parasitic-aware blockage polygons.
 3. The method ofclaim 1, wherein the physical information includes minimum and maximumwidths of the polygons of the detailed blockage structure represented bythe one or more parasitic-aware blockage polygons.
 4. The method ofclaim 1, wherein the physical information includes minimum and maximumspacings of the polygons of the detailed blockage structure representedby the one or more parasitic-aware blockage polygons.
 5. The method ofclaim 1, wherein the physical information includes average widths andspacings of the polygons of the detailed blockage structure representedby the one or more parasitic-aware blockage polygons.
 6. The method ofclaim 1, wherein the physical information includes standard deviationsof the polygons of the detailed blockage structure with respect to theone or more parasitic-aware blockage polygons.
 7. The method of claim 1,further comprising associating electrical information with each of theone or more parasitic-aware blockage polygons, wherein the electricalinformation defines electrical characteristics of the associated one ormore parasitic-aware blockage polygons.
 8. The method of claim 7,wherein the electrical characteristics comprise a capacitance errorintroduced by the one or more parasitic-aware blockage polygons.
 9. Themethod of claim 8, wherein the capacitance error specifies a differencebetween a first capacitance between the detailed blockage structure andone or more adjacent conductors and a second capacitance between theparasitic-aware blockage polygons and the one or more adjacentconductors.
 10. The method of claim 8, wherein the capacitance errorspecifies a difference between a first coupling capacitance between aplurality of conductors when located adjacent to the detailed blockagestructure and a second coupling capacitance between the plurality ofconductors when located adjacent to the parasitic-aware blockagepolygons.
 11. The method of claim 7, wherein the electricalcharacteristics comprise a resistance error introduced by the one ormore parasitic-aware blockage polygons.
 12. The method of claim 11,wherein the resistance error specifies a difference between a firstresistance of a conductor when fabricated adjacent to the detailedblockage structure, and a second resistance of the conductor whenfabricated adjacent to the one or more parasitic-aware blockagepolygons.
 13. A system for extracting parasitic capacitances associatedwith a detailed blockage structure, the system comprising: means forderiving one or more parasitic-aware blockage polygons from the detailedblockage structure, wherein each of the one or more parasitic-awareblockage polygons represents a plurality of polygons of the detailedblockage structure; means for associating physical information with eachof the one or more parasitic-aware blockage polygons, wherein thephysical information represents physical characteristics of therepresented plurality of polygons of the detailed blocking structure;and a processor that extracts parasitic capacitances that exist betweenthe detailed blocking structure and an adjacent interconnect structure,wherein the processor extracts the parasitic capacitances based on theone or more parasitic-aware blockage polygons and the associatedphysical information.
 14. The system of claim 13, further comprising:means for deriving electrical characteristics associated with each ofthe one or more parasitic-aware blockage polygons; and means forassociating the electrical characteristics with each of the one or moreparasitic-aware blockage polygons.
 15. The system of claim 14, whereinthe electrical characteristics specify capacitance errors introduced bythe one or more parasitic-aware blockage polygons with respect to thedetailed blockage structure.
 16. The system of claim 15, wherein one ofthe capacitance errors specifies a difference between a firstcapacitance between the detailed blockage structure and one or moreadjacent conductors and a second capacitance between the parasitic-awareblockage polygons and the one or more adjacent conductors.
 17. Thesystem of claim 13, wherein the electrical characteristics specify aresistance error introduced by the one or more parasitic-aware blockagepolygons.
 18. The system of claim 13, wherein the physical informationincludes a density of the detailed blockage structure with respect tothe one or more parasitic-aware blockage polygons.
 19. The system ofclaim 13, wherein the physical information includes minimum and maximumwidths of the polygons of the detailed blockage structure represented bythe one or more parasitic-aware blockage polygons.
 20. The system ofclaim 13, wherein the physical information includes minimum and maximumspacings of the polygons of the detailed blockage structure representedby the one or more parasitic-aware blockage polygons.
 21. The system ofclaim 13, wherein the physical information includes average widths andspacings of the polygons of the detailed blockage structure representedby the one or more parasitic-aware blockage polygons.
 22. The system ofclaim 13, wherein the physical information includes standard deviationsof the polygons of the detailed blockage structure with respect to theone or more parasitic-aware blockage polygons.